It is often desirable to improve the efficiency and comprehensiveness of manufacturing testing of computer components. To ensure fast and reliable operation of a computer, manufacturing testing of each part must include some form of speed testing to show that the component is operating within the specified timing parameters.
One common method of circuit testing is known as structural testing and is typically applied to a circuit as the circuit is produced at the factory. Generally, these tests are pre-developed by the test engineers and provided to the manufacturer for use during production of the design. As such, the test typically has no knowledge of the function of the circuit itself, and the circuit is typically viewed by the testing suite as a random set of flip-flop components and logic gates. However, because structural testing provides an indication that the manufacturing of the circuit is accurate at the intended speed, a more precise analysis of the circuit can be achieved through a more precise control of clock during structural testing.
In structural testing, an input test pattern is scanned into the logic of a digital circuit, a number of clock pulses are issued to advance the state, and then the final state is scanned out and compared to an expected output pattern to determine if the logic of the circuit is operating correctly. Generally, there are two types of structural testing performed on computer circuits. The first type of structural test, known as stuck-bit testing, issues a single clock pulse before scanning out the state and analyzing the result. This type of test is frequently used to determine manufacturing defects of the logic of the circuit which are speed independent. Another type of stuck-bit testing issues more than a single clock pulse. However, the clock pulse used in this type of testing is generally a far lower frequency than the intended operating frequency of the circuit under test.
The second type of structural test, known as at-speed test, issues two or more clock pulses at the expected operating frequency of the circuit. This type of test is used frequently to determine if the circuit operates correctly at the frequency of the clock signal. In other words, at-speed testing determines accuracy of the circuit based on the anticipated clock frequency for the circuit. Due to the differences in these types of testing, a testing device will perform two different test runs, which often requires the circuit designer to provide two different test patterns to the manufacturer. At-speed testing of circuits which require more than two clock pulses may suffer from negative voltage affects, known as voltage droop, which distorts the results of a multi-cycle test at the later cycles of the test, making the test results less accurate.
It is with these and other issues in mind that various aspects of the present disclosure were developed.